DK-DEV-5SGXEA7N【PDF 214/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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SV51008

2014.01.10

Dynamic OCT Control

7-23

taps then feed a multiplexer controlled by the UniPHY megafunction to select which clock phases are to be

used for that x4 or x 8 DQS group. Each group can use a different tap output from the read-leveling and

write-leveling delay chains to compensate for the different CK/CK# delay going into each device on the

module.

Figure 7-11: Write-Leveling Delay Chains and Multiplexers

There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can

only have one memory interface in each I/O sub-bank when you use the leveling delay chain.

Write clk

(-90 0 )

Write-Leveled DQS Clock

Write-Leveled DQ Clock

The – 90° write clock of the UniPHY IP feeds the write-leveling circuitry to produce the clock to generate

the DQS and DQ signals. During initialization, the UniPHY IP picks the correct write-leveled clock for the

DQS and DQ clocks for each DQ/DQS group after sweeping all the available clocks in the write calibration

process. The DQ clock output is – 90° phase-shifted compared to the DQS clock output.

The UniPHY IP dynamically calibrates the alignment for read and write leveling during the initialization

process.

Related Information

? Reference Material volume, External Memory Interface Handbook

Provides more information about the UniPHY IP.

? DDR2 and DDR3 SDRAM Board Design Guidelines chapter, External Memory Interface Handbook

Provides layout guidelines for DDR3 SDRAM interface.

Dynamic OCT Control

The dynamic OCT control block includes all the registers that are required to dynamically turn the on-chip

parallel termination (R T OCT) on during a read and turn R T OCT off during a write.

Figure 7-12: Dynamic OCT Control Block for Stratix V Devices

OCT Control Path

OCT Control

2

DFF

DFF

OCT Enable

OCT Half-Rate Clock

HDR Block

Resynchronization

Registers

Write Clock

The write clock comes from either the PLL or the write-

leveling delay chain.

External Memory Interfaces in Stratix V Devices

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